Processors have input and output lines for communication of signals with other devices. Theses input and output lines are grouped into busses for communication of signals in parallel or serial communication. Drivers are connected to the input and/or output lines to drive signals on these lines. Often more than one driver is connected to a single line and the line is multiplexed to accept signals from different drivers. One form of multiplexing is accomplished by time dividing the input to the signal line so that each driver is provide one or more time slots for driving the signal line.
For example, as illustrated in FIG. 1, the digital telephony interface 5 to a DSP 6 in a voice over packet application is via the multichannel buffered serial port interface 7. The serial TDM bus 8 typically has several different sources driving the BDX signal from the DSPs 6 in the core 9 to the telephony circuit 5. Each DSP is assigned one or more timeslots on the time division multiplexed bus 8 and drives the BDX signal during this defined period. When a DSP is not driving the BDX signal, that DSP is in a high impedance state to allow another source to drive the BDX signal. There is a finite amount of time required to allow the first source to stop driving the BDX signal so that the next source can start driving the BDX signal. This time is required to allow the first source to achieve a high impedance state. The time required to switch sources limits the frequency (bandwidth) of the bus. Any clock frequency that is too high will cause contention on the bus.
Presently this problem is addressed by using logic gates to OR the signals together. This method has a significant disadvantage in that pull-down resistors must be used to drive the inactive signals low to the OR gate input. For high frequency busses, these pull-down resistors must have rather small resistances (200-500 Ohms) to pull the signal down quickly enough. This causes significant and unwanted power consumption.